TDA837x family
I2C-bus controlled economy PAL/NTSC and NTSC
TV-processors

GENERAL DESCRIPTION
The various versions of the TDA837x series are I
2C-bus
controlled single-chip TV processors which are intended to
be applied in PAL/NTSC (TDA8374 and TDA8375) and
NTSC (TDA8373 and TDA8377) television receivers.
All ICs are available in an SDIP56 package and some
versions are also available in a QFP64 package. The ICs
are pin compatible so that with one application board
NTSC and PAL/NTSC (or multistandard together with the
SECAM decoder TDA8395) receivers can be built.
Functionally this IC series is split in to 2 categories:
• Versions intended to be used in economy TV receivers
with all basic functions
• Versions with additional functions such as E-W
geometry control, horizontal and vertical zoom function
and YUV interface which are intended for TV receivers
with 110° picture tubes.
The various type numbers are given in Table 1.
The detailed differences between the various ICs are
given in Table 2.